Reversible logic implementation of AES algorithm
Kamalika Datta, Vivek Kumar Shrivastav, Indranil Sengupta, Hafizur Rahaman · 2013
Since the selection of the Rijndael cryptosystem as a new Advanced Encryption Standard (AES) in 2000, many hardware implementations of AES have been reported. Some of these implementations are optimized for speed, some for area, some for reconfigurability, and some for low-power applications. Again, reversible logic synthesis methodologies have drawn the attention of researchers in recent times, mainly with the prospect of quantum computing becoming a reality, and the potential of reversible logic circuits for providing ultra low-power implementations. Although many of the cryptographic primitives are inherently reversible by nature, very little work has been done towards reversible logic implementations of the same. The only published works relate to reversible implementations of Montgomery multiplication algorithm, which has applications in cryptography. The present paper, possibly for the first time, presents a reversible logic implementation of a block cipher, namely, 128-bit AES. The various AES functional blocks have been synthesized using reversible gates, using which an overall reversible architecture has been proposed. The pipelined version as suggested can only be used in the Electronic Code Book (ECB) mode. The hardware complexity of the implementation has been evaluated using the number of reversible gates required and the quantum cost.