An efficient serial distributed arithmetic algorithm for FPGA implementation of digital up conversion
Tania Tareq Salim, J. C. DEVLIN, J. Whittington, M. Ishaq Bhatti · Complexity · 2005
This article deals with a computationally efficient serial distributed arithmetic algorithm producing a device efficient field programmable gate array implementation. The proposed algorithm takes half the computations time as compared to the conventional symmetric algorithms. The algorithm is analyzed for a direct conversion transmitter of ionospheric radar. Matching and buffering criterion are used to reduce the arithmetic process. The algorithm can be extended to applications with similar characteristics, particularly for System On Chip (SOC) techniques. © 2005 Wiley Periodicals, Inc. Complexity 11: 24–29, 2005