VT Matrix Multiply Design for MEMOCODE '07
Eric Simpson, Pengyuan Yu, Patrick R. Schaumont, Sumit Ahuja, Sandeep K. Shukla · 2007
This design presents a system optimized for complex matrix multiplications on the XUP Virtex-II board. Utilizing the GEZEL HW/SW co-simulation environment, the resulting system achieves ~25x speedup over a standard software only implementation. Further system level optimization (with DMA) results in the same coprocessor being speedup by at least another order of magnitude.