High-Speed Algorithms and Architectures for Range Reduction Computation
Francisco J. Jaime, Miguel A. Sanchez, Javier Hormigo, Julio Villalba, Emilio L. Zapata · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2009
Range reduction is a crucial step for accuracy in trigonometric functions evaluation. This paper shows and compares a set of algorithms for additive range reduction computation and their corresponding application-specific integrated circuit implementations (ensuring an accuracy of one unit in the last place). A word-serial architecture implementation has been used as a reference for clearer comparisons. Besides, a new table-based pipelined architecture for range reduction has also been proposed.