Low area ECC implementation on FPGA
Zia Uddin Ahamed Khan, Mohammed Benaissa · 2013
In this paper, a new compact standalone design of an Elliptic Curve Cryptography (ECC) processor over Galois field GF (2163) is analysed and implemented on FPGA for the three most popular point multiplication algorithms (the basic binary, Montgomery, and Frobenius map). We demonstrate new concurrency in point addition and point doubling together with novel flexible memory and efficient arithmetic units. We investigate area-time and area2-time performances exploiting a very compact bit/digit serial multiplier. We include a very low cost 8-bit input-output interface that can be embedded with 8-bit processors for low area applications. We compare our results with relevant works on different FPGAs (Virtex (V, Ve, V2, V2p, V4, V5) and Spartan (S3 and S6)). Our Montgomery implementation on V5 shows the best result achieving 0.11 ms for an ECC point multiplication with only 473 slices in area. To our knowledge, the proposed architecture achieves the best area2-time metric performance on FPGA to date.