Linear equivalence of certain BRM shift-register sequences
W.G. Chambers, S.M. Jennings · Electronics Letters · 1984
A theorem given by Albert is used to show that if a shift register of length m is used to clock another shift register of length n through a binary rate-multiplier, then it can easily be arranged that the output has a linear equivalence of (2m − 1)n and a period of (2m − 1)(2n − 1).