Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture
Juinn-Dar Huang, Chia-I CHEN, Yen-Ting Lin, Wan-Ling HSU · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · 2011
In deep-submicron era, wire delay is becoming a bottleneck while pursuing even higher system clock speed. Several distributed register (DR) architectures have been proposed to cope with this problem by keeping most wires local. In this article, we propose a new resource-constrained communication synthesis algorithm for optimizing both inter-island connections (IICs) and latency targeting on distributed register-file microarchitecture (DRFM). The experimental results show that up to 24.7% and 12.7% reduction on IIC and latency can be achieved respectively as compared to the previous work.