A New Architecture for H.264 Variable Block Size Motion Estimation
Chunlei Yang, Rong Luo, Huazhong Yang · Conference proceedings · 2006
In an H.264 video encoder, motion estimation (ME) is the most time-consuming component. Several fast ME algorithms have been proposed to reduce the complexity of integer pixel ME (IME) computation, but few of them considered IME and fractional pixel ME (FME) together. Given the possibility of performance improvement through designing both IME and FME at the same time, a new hardware architecture is proposed for variable block size motion estimation with full search at 1/4 pixel accuracy. With the search range (SR) of [-20, +19] in both horizontal and vertical direction, the new architecture will save more than 50% computation time compared with full search algorithm (FS), while the cost is 50% increase of the sum of absolute differences (SAD) in average. The hardware implementation can achieve real-time operation at a frequency of 15MHz for CIF format frame at 30Hz.