Temporal Logic Based Hierarchical Test Generationfor Sequential VLSI Circuits
Anand V. Hudli, Raghu V. Hudli · VLSI design · 1993
Test generation for sequential VLSI circuits has remained a difficult problem to solve. The difficulty arises because of reasoning about temporal behavior of sequential circuits. We use temporal logic to model digital circuits. Temporal Logic can model circuits hierarchically. A set of heuristics is given to aid during test generation. A hierarchical test generation algorithm is proposed.