Achieving High Throughput in High-Radix Switch
Ming Fang, Chen Song-qiao, Kefei Wang · 2011
Current research and trends reveals that high-radix switches can remarkably lower down the network diameter and switch count of interconnection network in high performance computers, and it is much valuable in saving packet latency, cost and power consumption. HOL blocking limits the throughput of an N×N crossbar to less than 58% and this can be even worse in high radix switches because most technologies claimed as could eliminate HOL blocking cannot be scalable to high radix switches. In this paper, a new efficient architecture for high-radix switches is proposed. The architecture, referred to as Hierarchical Asymmetric Crossbar (HAC), relies on one simple but important fact that in an asymmetric crossbar, which input ports much less than output ports, effect of HOL blocking on crossbar throughput is very low or negligible. Thus a HAC architecture N×N high radix switch can be divided into two levels, the first level includes N/m smaller m×N asymmetric crossbars, and the second level includes N small N/m×1 multiplexer. A 32×32 HAC high radix switch prototype, based on 4×32 asymmetric small crossbars, is introduced in the paper. Clock cycle simulation reveals that in such a switch the impact of HOL blocking is nearly all eliminated and the switch throughput can be as high as 94%.