Hybrid clock synchronization: Conditions for existence of a steady state in a mesh network
Haruki Yahata · Electronics and Communications in Japan (Part I Communications) · 1998
A hybrid clock synchronization technique, combining master-slave and mutual synchronization schemes and used to synchronize the clock of a mesh-type area network (such as a LAN) to the clock of a wide-area network (such as a WAN), is advantageous from the reliability viewpoint. A sufficient condition is derived for the existence of a stable phase state when hybrid synchronization is employed in a mesh-type area network. For multiple-input second-order PLLs with sinusoidal or triangular phase comparator characteristics used in a clock synchronization circuit, let kVCi be the ratio of the difference between the input frequency from the wide-area network and the PLLs center frequency to the PLL's maximum lock range, and let KSi be the sum of the clock gains for each input. Then, a sufficiently stable clock synchronization system is obtained by considering a network structure composed of nodes such as one dominating clock gain such that KiP satisfies KiP ≥ KSi (1 + |kVCi|)/2. A ring connection of PLLs with clock input from the wide-area network and the subordinate connection of other PLLs to the ring-connected PPLs is one of the most suitable network structures to maintain clock synchronization, even in the case of one-point failure in a network. © 1998 Scripta Technica, Electron Comm Jpn Pt 1, 81(11): 77–89, 1998