Low complexity semi–systolic multiplication architecture over GF(2m)
Se-Hyu Choi, Keon-Jik Lee · IEICE Electronics Express · 2014
This paper presents a semi-systolic Montgomery multiplier based on the redundant basis representation of the finite field elements. The proposed multiplier has less hardware and time complexities compared to related multipliers. We also propose a serial systolic Montgomery multiplier that can be applied well in space-limited hardware. Furthermore, a simple inversion based on the proposed scheme is presented.