Performance and scalability of parallel PIC and fluid codes on Xeon Phi based supercomputers
Eric Hallman, Kristian C. Beckwith, Peter Holmes Stoltz · 2014
Summary form only given. We present results from performance tests for 3 highly parallel numerical simulation codes on the Texas Advanced Computing Center's Stampede Supercomputer. Stampede utilizes the Intel Xeon Phi architecture, which includes the Many Integrated Core (MIC) co-processors, programmed with a standard x86 instruction set.