Uniform Synthesis of Sequential Circuits†
Jeffrey David Ullman, Peter D. Weiner · Bell System Technical Journal · 1969
In this paper we consider the synthesis of sequential machines by networks of a fixed module with delay. We show that every binary input n state sequential machine has an isomorphic realization using at most p copies of a module with 2r + 1 inputs, where p is the smaller of${2r \over 2r - 1} (n^{1+log r^2} + 4n^{1+log r^4)$and$r2^[n/r]$. ([x] is the smallest integer ≧ x.)