A 30fps stereo matching processor based on belief propagation with disparity-parallel PE array architecture
Jun-Young Park, Seungjin Lee, Hoi‐Jun Yoo · 2010
In this paper, we propose a real-time stereo matching processor based on the belief propagation algorithm. Computationally complex message construction is accelerated by a disparity-parallel PE array architecture, which calculates messages for all disparity levels (1-32) in parallel. A tile-based belief propagation approach reduces the on-chip memory requirements by 95.4% compared to the previous works. In addition, a two-level on-chip buffer and memory access pipelining enable high PE utilization of 89%. As a result, the message construction rate of the PEs is increased by 6.45x compared to previous works. The fabricated processor in a 0.18um CMOS process achieves 30 fps performance for QVGA (320×240) video inputs at 200 MHz operating frequency.