What is timing-closure in high-end FPGAs?
Angela Sutton, Jeff Garrison · ACM SIGDA Newsletter · 2008
Timing-closure is a growing concern for FPGA designers, particularly with the recent introduction of multi-million gate architectures fabricated at the 90 nm and 65 nm technology nodes. It is not sufficient for a timing-closure solution - the entire flow, including synthesis - to meet only the required timing; such a solution must also minimize the number of time-consuming synthesis-place-route iterations and provide results that remain stable across multiple physical synthesis runs and during final routing.