ElastiStore: an elastic buffer architecture for network-on-chip routers
Ioannis Seitanidis, Αναστάσιος Ψαρράς, Giorgos Dimitrakopoulos, Chrysostomos A. Nicopoulos · 2014
Abstract—The design of scalable Network-on-Chip (NoC) ar-chitectures calls for new implementations that achieve high-throughput and low-latency operation, without exceeding the stringent area-energy constraints of modern Systems-on-Chip (SoC). The router’s buffer architecture is a critical design aspect that affects both network-wide performance and implementation characteristics. In this paper, we extend Elastic Buffer (EB) architectures to support multiple Virtual Channels (VC) and we derive ElastiStore, a novel lightweight elastic buffer architec-ture that minimizes buffering requirements, without sacrificing performance. The integration of the proposed elastic buffering scheme in the NoC router enables the design of new router architectures – both single-cycle and two-stage pipelined – which offer the same performance as baseline VC-based routers, albeit at a significantly lower area/power cost. I.