Evaluation and performance analysis of energy efficient wireless NoC architecture
Dominic DiTomaso, Soumyasanta Laha, Avinash Kodi, Savaş Kaya, David W. Matolak · 2012
As Network-on-Chip (NoC) architectures become more relevant with an increasing number of cores on a chip, research into emerging technologies and devices to replace power hungry global metallic interconnects has become critical. In this paper, we propose a practical wireless architecture called GLOW, a global wireless interconnect for NoCs. With our ultra-low power transceivers centered at a 100 GHz carrier frequency, we present a wireless topology with a maximum bandwidth of 80 GHz. Both frequency and spatial division multiplexing (FDM and SDM) are used in GLOW on a near-term 64-core architecture. We are able to achieve a power savings up to 56% compared to mesh, torus and CMesh while improving speedup by 2.1× on average on real application benchmarks.