Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips
Weng‐Geng Ho, Kwen‐Siong Chong, Bah‐Hwee Gwee, Joseph Sylvester Chang · 2014
We propose an Asynchronous-to-Synchronous Interface Controller (A2S-IC) with low delay-variation towards Process, Voltage and Temperature (PVT) variations for sub-threshold/near-threshold operation in low power applications. This A2S-IC is targeted for a full-range Dynamic Voltage Scaling (DVS) Global-Asynchronous-Local-Synchronous (GALS) Network-on-Chip (NoC). There are three key attributes in this proposed A2S-IC. First, it is realized using static-logic (over dynamic-logic), hence is more appropriate for DVS (and sub-threshold operation). Second, it is implemented using gate-level standard-cell to simplify the implementation efforts. Third, it is designed to share some internal nodes, hence reducing the redundant switching for data validity checking. The proposed A2S-IC is compared against its reported dynamic-logic counterpart; both are implemented in the same 65nm CMOS process. Based on the simulations conducted at 27 C, our proposed A2S-IC is more throughput-efficient at near- and sub-threshold operations, featuring ~19% and ~66% faster throughput at FDD=0.5V and FDD=0.3V respectively. When the temperature variation (0°C to 100°C) is considered at the sub-threshold operation, the proposed A2S-IC demonstrates 140% faster throughput than the reported design, the former only features up to 1.6x delay-variation but the latter exhibits up to 4x delay-variation. The proposed A2S-IC is able to operate at the voltage as low as 0.15V (as opposed to 0.3V for the reported design).