New systolic arrays for C+AB/sup 2/, inversion, and division in GF(2/sup m/)
Jyh-Huei Guo, Chin-Liang Wang · IEEE Transactions on Computers · 2000
In this paper, we present a new parallel-in parallel-out systolic array with unidirectional data flow for performing the power-sum operation C+AB/sup 2/ in finite fields GF(2/sup m/). The architecture employs the standard basis representation and can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle. It is highly regular, modular, and, thus, well-suited to VLSI implementation. As compared to a previous systolic power-sum circuit with bidirectional data flow and the same throughput performance, the proposed one has smaller latency, consumes less chip area, and can more easily incorporate fault-tolerant design. Based on the new power-sum circuit, we also propose a parallel-in parallel-out systolic array with the maximum throughput for computing inverses/divisions in GF(2/sup m/). The proposed systolic divider gains advantages over an existing system with the same throughput performance in terms of chip area, latency, and fault tolerance.