Activity-sensitive architectural power analysis for the control path
Paul E. Landman, Jan M. Rabaey · 1995
Prompted by demands for portability and low-cost packaging, the electronics industry has begun to view power consumption as a critical design criteria. As such there is a growing need for tools that can accurately predict power consumption early in the design process. Many high-level power analysis tools don’t adequately model activity, however, leading to inaccurate results. In a previ-ous publication, we introduced architecture-level power analysis techniques for datapath and memory modeling. This paper focuses on the control path, describing a novel power analysis strategy known as the Activity-Based Control (ABC) model. Architecture-level estimates are then compared to switch-level simulations of three chips: a divider, a speech recognition controller, and a microprocessor. The average error observed in the control path power estimates is 13 % with a maximum error of 29%. 1