Design and evaluation of decimal array multipliers
Saeid Gorgin, Ghassem Jaberipur, Behrooz Parhami · 2009
Hardware support for decimal arithmetic has become an important focal point, both in the research arena and in commercial processor developments. Like their binary counterparts, decimal multipliers can be designed in a variety of ways, offering area and speed trade-offs. Pipelined array multipliers support high throughput, making them attractive in multiply-intensive applications. We propose two different architectures for decimal array multipliers based on (1) precomputed multiples and (2) decimal digit-multipliers. We compare the VLSI area and delay parameters of the resulting array multiplier designs with each other and with those of binary array multipliers covering the same range of inputs.