Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division
Manish Kumar Jaiswal, Ray C. C. Cheung, S. Balakrishnan, Kolin Paul · 2014
This paper presents a dynamically configurable and area-efficient multi-precision architecture for Floating Point (FP) division. FP division is a core arithmetic in scientific and engineering domain. We propose an architecture for double precision (DP) division which is also capable of processing dual (two-parallel) single precision (SP) computation, named as DPdSP FP divider. The architecture is based on series expansion methodology ofcomputing division. Key components involved in the floatingpoint division architecture are re-designed in order to efficiently enable the resource sharing and tune the data-path for processing both precision operands with minimum hardware overhead. We have targeted the proposed architecture using "OSUcells Cell Library" 0.18μm technology ASIC implementation. Compared to a standalone double precision divider, the proposed dual modeunified architecture needs ≈ 7% extra hardware, with ≈ 5% delay overhead. When compared to the previous work in literature, the proposed dual mode architecture out-perform them in terms of required area, throughput, and area × delay, has smaller area & delay overhead over only DP divider, and has more computational support.