The microarchitecture of the synergistic processor for a cell processor
Brian Flachs, Saki Asano, S.H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, T. Le, Peichun Liu, Jens Leenstra, J. S. Liberty, B. Michael, Hwa-Joon Oh, Silvia Melitta Mueller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel Brokenshire, Mohammad Peyravian, V. To · IEEE Journal of Solid-State Circuits · 2005
This paper describes an 11 FO4 streaming data processor in the IBM 90-nm SOI-low-k process. The dual-issue, four-way SIMD processor emphasizes achievable performance per area and power. Software controls most aspects of data movement and instruction flow to improve memory system performance and core performance density. The design minimizes instruction latency while providing for fine grain clock control to reduce power.