Reduced-routing complexity decoder for high-rate QC-LDPC codes
Yong Niu, Zhenyu Xiao, Depeng Jin, Li Su, Lieguang Zeng · 2011 International Conference on Computational Problem-Solving (ICCP) · 2011
This paper presents a high-throughput and routing complexity reduced decoder for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes in the high rate wireless personal area network applications (WPAN). Our selected code is the rate-1/2 QC-LDPC code in IEEE P802.11ad/D1.0. A new decoder architecture is proposed. The message paths between variable nodes and check nodes are constructed by a fixed wire network. Compared to the fully parallel architecture, routing complexity of the new architecture is reduced greatly. The decoder is implemented using FPGA, and a data rate of 1.21 Gbps can be achieved in the air.