Low-power mapping of behavioral arrays to multiple memories
Preeti Ranjan Panda, Nikil D. Dutt · 1996
Large data arrays in behavioral specifications are usually mapped to off-chip memories during system synthesis. We address the problem of system power reduction through transition count minimization on the address bus during memory accesses, when mapping behavioral arrays to multiple memory modules drawn from a library. We formulate the problem as three logical-tophysical memory mapping subtasks, provide algorithms for each subtask, and present experiments that demonstrate the transition count reductions based on our approach. Our experiments show a transition count reduction by a factor of 1.5--6.7 over a straightforward mapping scheme. 1 Introduction and Related Work The increasing demand for portable electronic equipment in recent times has led to extensive research in low power design techniques. Applications such as portable communicationsand multimedia drive the trend towards reduction in power dissipation in VLSI systems. Minimizing memory-related power forms an important task...