Partially shared variables and hierarchical shared memory multiprocessor architectures
D.N. Jayasimha · 1992
Latency and synchronization overheads have been identified as two fundamental problems in large-scale shared memory multiprocessors. The notion of partial sharing of variables is introduced, and architectures based on hierarchical memories which exploit this notion of partial sharing to reduce the latency and synchronization overheads significantly are suggested. A particular class of architectures, the tree structure, hierarchical memory multiprocessor architectures (THMMs), is examined by suggesting an implementation and considering the execution and the performance of several well-known applications such as matrix multiplication, solution of partial differential equations, solution of linear recurrence relations, barrier synchronization, and reduction operations. Speedup and cost figures for these examples are compared when executing on the THMM and on a conventional memory multiprocessor.>