Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs
Byungil Jeong, Sungjoo Yoo, Sunghyun Lee, Ki‐Young Choi · 2000
This paper presents a method for hardware-softw are cosynthesis with run-time incrementally recon gurable FPGAs.T o reduce the run-time o v erhead of recon guring FPGAs, we present a concept called early partial recon guration (EPR) which minimizes the ov erhead by performing recon guration for an operation (or a task in our terms) mapped to an FPGA as early as possible so that the operation is ready to start when its execution is requested.F or further reduction of the ov erhead,w ein tegrate the incremental reconguration (IR) of FPGAs with the EPR concept.We present an ILP formulation and an eÆcient heuristic algorithm based on the EPR and IR concepts.Experiments on embedded system examples and syn thetic examples show the eÆciency of the proposed method