Asynchronous system synthesis based on direct mapping using VHDL and Petri nets
Delong Shang, Frank Burns, AM Koelmans, Alex Yakovlev, Fei Xia · IEE Proceedings - Computers and Digital Techniques · 2004
A technique is proposed to synthesise system behavioural specifications written in VHDL into speed-independent asynchronous circuits constructed using David cells. This technique combines the advantages of logic synthesis and syntax-directed translation techniques. Coloured Petri nets and labelled Petri nets are used as intermediate formats for datapath and control representation. Speed-independent asynchronous circuits are obtained from these nets via direct translation. Several examples demonstrate the viability of the technique, which produces superior results compared with other ones.