High-level parallel architecture for a rule-based system
Ramesh K. Karne, Arun K. Sood · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1991
A parallel architecture for rule-based systems is generally based on techniques that reduce the execution time of a production cycle, match- select-act cycle. With these techniques, speedups in rule-based systems are limited to tenfold. We investigate a new approach to achieve higher speedups by developing a computer architecture that exploits parallelism at much higher levels. This high-level parallel architecture is based on a semantic network representation and message passing. This architecture closes the semantic-gap that exists between the application and its implementation and yields higher speedups. To demonstrate our approach, we have chosen the VLSI architecture simulation application which has inherent parallelism and demands large execution times on conventional computers. We performed functional simulations for two applications and measured close to linear speedups. In this paper, we present the applications, knowledge representation scheme, architecture suitable for this set of applications, and speedup measurements.