A CMOS VAX microprocessor with on-chip cache and memory management
David W. Archer, D.R. Deverell, T.F. Fox, P.E. Gronowski, A.K. Jain, M. Leary, D.G. Miner, A. Olesin, S.D. Persels, P.I. Rubinfeld, Robert M. Supnik · IEEE Journal of Solid-State Circuits · 1987
A single-chip 32-b microprocessor designed in a 2-/spl mu/m (drawn) CMOS process with two layers of metal interconnect is described. The microprocessor implements the VAX architecture. A one-transistor dynamic RAM cell is used to build a 1-kbyte instruction and data cache. The chip contains 134000 transistors, is 9.4/spl times/9.7 mm/SUP 2/ large, operates at 5.0 V, and dissipates 1.5 W.