Gate-level test generation for sequential circuits
Kwang-Ting Tim Cheng · ACM Transactions on Design Automation of Electronic Systems · 1996
This paper discusses the gate-level automatic test pattern generation (ATPG) methods and techniques for sequential circuits. The basic concepts, examples, advantages, and limitations of representative methods are reviewed in detail. The relationship between gate-level sequential circuit ATPG and the partial scan design is also discussed.