A multiple fault-tolerant processor network architecture for pipeline computing
Jerzy Tyszer · IEEE Transactions on Computers · 1988
Certain fault-tolerant multiprocessor networks that can emulate linear array interconnections are considered. The system is fault tolerant of (m-1) node and link failures. One of the particularly attractive features of this network is that it allows for a linear array structure starting with any node even in spite of (m-2) faults. The configuration algorithm is fully distributed, and is performed on the basis of test results obtained from nonfaulty processors only. A simple fault identification procedure is developed using the above routing algorithm.>