VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding
T. Masaki, Y. Morimoto, Takao Onoye, Isao Shirakawa · IEEE Transactions on Circuits and Systems for Video Technology · 1995
An MPEG2 video decoder core dedicated to MP@HL (Main Profile at High Level) images is described with the main theme focused on an inverse discrete cosine transformer and a motion compensator. By means of various novel architectures, the inverse discrete cosine transformer achieves a high throughput, and the motion compensator performs different types of picture prediction modes employed by the MPEG2 algorithm. The decoder core, implemented in the total chip area of 22.0 mm/sup 2/ by a 0.6-/spl mu/m triple-metal CMOS technology, processes a macroblock within 3.84 /spl mu/s, and therefore is capable of decoding HDTV (1920/spl times/1152 pels) images in real time.>