A 1.4 ns/64 kb RAM with 85 ps/3680 logic gate array
Masaomi Kimoto, Haruo Shimizu, Yuya Ito, Kenta Kohno, M. Ikeda, T. Deguchi, Nobuko Fukuda, K. Ueda, Shoji Harada, K. Kubota · 1989
The authors have developed an ECL (emitter-coupled logic) 64-kb RAM with 3680-gate logic gate array LSI using bipolar technology. The address access time is 1.4 ns (typical), clock access time is 1.8 ns (typical), and the propagation delay of the logic rate is 85 ps. The chip is 13.5 mm2in area and packaged in a 462-pin grid array