A hardware accelerated system for deep packet inspection
Adarsha Rao, Pramod Udupa · 2010
We implemented a hardware accelerated system for deep packet inspection. The proposed system makes use of operation level and connection level parallelism to achieve a maximum processing rate of 595.2Mb/s. The system supports 25 mandatory patterns running at 125 MHz on a Xilinx Virtex 5 FPGA.