Two hardware designs of BLAKE-256 based on final round tweak
Muh Syafiq Irsyadi, Shûichi Ichikawa · 2011
This paper presents two implementations of BLAKE hash family algorithm that has been selected as one of the SHA-3 competition finalist. The first implementation is a modification from the implementation of Beuchat et al. which significantly reduces the required ROM size up to 36% from the original requirement with small trade-off in additional logic circuit. The second implementation is an extension from Half-G structure that was designed to be flexible for different kinds of application. The highly compact BLAKE-256 design uses 356 LE and 9776 bits of memory when implemented in Cyclone III FPGA. Regular data-path design requires 369 slices and 1 memory block in Virtex 5 FPGA. Both designs are fully autonomous, which means that these designs do not require any additional memory or logic outside its system.