The iCORE/spl trade/ 520 MHz synthesizable CPU core
Nicholas Richardson, Lun Huang, Rakib Hossain, Tommy Zounes, Naresh Soni, Jonathan Lewis · 2002
This paper describes a new implementation of the ST20-C2 CPU architecture. The design involves an eight-stage pipeline with hardware support to execute up to three instructions in a cycle. Branch prediction is based on a 2-bit predictor scheme with a 1024-entry Branch History Table, a 64-entry Branch Target Buffer and a 4-entry Return Stack. The implementation of all blocks in the processor was based on synthesized logic generation and automatic place and route. The full design of the CPU from microarchitectural investigations to layout required approximately 8-man years. The CPU core, without the caches, has an area of approximately 1.5 mm/sup 2/ in a 6-metal 0.18 /spl mu/m CMOS process. The design operates up to 520 MHz at 1.8 V, among the highest reported speeds for a synthesized CPU core.