Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs
Kazuhiko Terada, Hiroyuki Uzawa, Namiko Ikeda, Satoshi Shigematsu, Nobuyuki Tanaka, 正美 浦野 · 2012
Verification of the hardware/software functions of a 10-Gbit/s-class large-scale network systems-on-a-chip (NW SoC) requires the use of multiple field programmable gate array (FPGA) devices. We propose two schemes for the efficient mapping of the design data of the NW SoC into FPGA devices. We implemented practical NW SoC design data for FPGA devices, and evaluated the effectiveness of the schemes. The results show that the proposed schemes can reduce the number of wires by 13% and improve the register access cycle time by 28%.