VLSI architecture of signal processing chip set for 42-inch DC PDP HDTV receiver
H. Kokubun, Yoshimichi Takano, Takashi Yamamoto, Keiji Ishii, Taiichiro Kurita · IEEE Transactions on Consumer Electronics · 1998
A signal processing chip set for 42-inch DC PDP HDTV receivers has been developed. Four kinds of signal processing LSIs are fabricated with a semi-custom LSI design and 0.35 /spl mu/m triple-metal CMOS technology. This paper describes the architecture of the LSI chip set and new circuit configurations to improve the picture quality. The chip set has enabled a practical PDP HDTV receiver to be fabricated.