A 2.84W 16port Switch ASIC for high performance computing systems
Hua Shen, Ding-shan You, Like Liu, Jia Ni Yang, Xiaoxiao Jiang · 2009
The chip's structure, design trade-off, and physical implementation with power optimization of a 2.84 W switch ASIC, which is targeted for large scale parallel computing systems, are introduced in this paper. The chip supports not only multi-layer, multi-function packet switching with high throughput and low latency, but also provides advanced global barrier process accelerating between its 16 full-duplex ports. At 156.25 Mhz, the chip has 83.2 ns zero-load latency, 80 Gbps port-switching and 240 Gbps internal packet switching capacity with port's data throughput at 2 × 2.5 Gbps. The ASIC has been taped-out with 0.18 um/6metal CMOS technology, and has about 20 million transistors; 12.39 mm × 12.39 mm die size; with 1053 pin flip-chip package. The first pass silicon of this switch ASIC has successfully passed DFT, functional and system level testing.