Codes to reduce switching transients across VLSI I/O pins
Arvin Park, R. A. Maeder · ACM SIGARCH Computer Architecture News · 1992
We develop a coding scheme that reduces switching transients by limiting the number of lines that simultaneously switch during transmission of address and data information over the I/O pins of a VLSI chip, or the lines of a system bus. The maximum number of lines that simultaneously switch can be reduced by a factor of two using simple and fast circuitry for encoding and decoding.