Parallel testing for pattern-sensitive faults in semiconductor random-access memories
Pinaki Mazumder, Janak H. Patel · IEEE Transactions on Computers · 1989
A design strategy is presented for efficient and comprehensive parallel testing of high-density, MOS random-access memories (RAMs). Parallel test algorithms for RAMs have been developed on the basis of this design-for-testability approach for a broad class of pattern-sensitive faults. Two algorithms which are significantly more efficient than previous approaches are examined. The first algorithm detects the static and dynamic pattern-sensitive faults over a neighborhood of five cells. The second algorithm tests the symmetric pattern-sensitive faults over a neighborhood of nine cells. It tests an n-bit RAM organized as a square root n* square root n array in 97 square root n memory cycles. The design-for-testability approach modifies the existing RAM architecture very little, so that it can be implemented very easily. The additional overhead is only about 2 square root n transistors. The low overhead allows high reliability, and the additional circuit for each bit line can fit within the 3 lambda -to-6 lambda pitch width in a high-density, single-transistor dynamic RAM. Although the algorithm is designed to detect pattern-sensitive faults, the modified architecture can be readily used to speed up other conventional algorithms of linear complexity by a factor of O( square root n).>