A Novel Design and FPGA Based Implementation of A Byte-wise ORG Code Generator Chip using VHDL
Mohd Hasan, Shuja Ahmad Abbasi, Kampan Nabi Khan, Syed Ali Faraz · IETE Technical Review · 1998
FPGA based implementation and VHDL based design of a reconfigurable CRC code generator chip with a CRC of 16 bits using a powerful byte-wise rather than the conventional bit-wise algorithm is presented. The hardware design and simulation has been carried out with the help of high level design environment tools using VHDL. The circuit has been simulated and implemented in FPGA. The approach adopted is absolutely general and can be extended to other types of CRC's as well. The CRC chip has all the inherent advantages of FPGA and has applications in areas such as error detection and correction in data communication and signature analysis.