Exploring reconfigurable architectures for explicit finite difference option pricing models
Qiwei Jin, David Barrie Thomas, Wayne W. Luk · 2009
This paper explores the application of reconfigurable hardware and graphics processing units (GPUs) to the acceleration of financial computation using the finite difference (FD) method. A parallel pipelined architecture has been developed to support concurrent valuation of independent options with high pricing throughput. Our FPGA implementation running at 106 MHz on an xc4vlx160 device demonstrates a speed up of 12 times over a Pentium 4 processor at 3.6 GHz in single-precision arithmetic; while the FPGA is 3.6 times slower than a Tesla C1060 240-Core GPU at 1.3 GHz, it is 9 times more energy efficient.