Regular architectures of a two-input one-output digital controller
Shuenn‐Shyang Wang · International Journal of Systems Science · 1991
Regular architectures of a two-input one-output digital controller are developed by applying the signal flow graph systolization procedure. These systolic architectures not only take into account the computational delay involved in computing the control law so that the input and outputs are exactly synchronized, but also possess the essential features of regularity, modularity and local interconnection which are important for VLSI implementation.