VHDL switch level fault simulation
C.A. Ryan, Joseph G. Tront · European Design Automation Conference · 1994
Switch level faults, as opposed to traditional gate level faults, can more accurately model physical faults found in an integrated circuit. This paper presents a novel VHDL switch level fault simulator. The simulator implementation uses 9-valued logic, N and P-type switch state tables, a minimum operation, and a switch level extension to parallel fault single pattern fault simulation. The advantages of this technique and hardware description language implementation are fault modeling accuracy and a straight forward implementation that compiles switches and faults to VHDL code.