A systematic methodology for mapping DSP algorithms onto multilevel array architectures
Dimitrios Soudris, Panagiotis Georgakopoulos, C.E. Goutis · International Journal of Electronics · 1995
In this paper, a systematic graph-based methodology for designing systolic arrays, which can perform concurrently, is introduced. Partitioning a DSP iterative algorithm into a number of sub-algorithms, we describe each of them, along with their interdependences, with a set of Uniform Recurrent Equations. Alternative architectures can be designed by mapping the dependence graph of the algorithm onto hardware. The main feature of the proposed architectures is the significant reduction of the computation time of the algorithm.