Reducing the Power Consumption of the AES S-Box by SSC
Jinyi Zhang, Qinghua Zuo, Tianbao Zhang · 2007
The advanced encryption standard (AES) algorithm has been accepted as the default choice in present security services. The S-box as the key part in AES plays an important role for low-power design in the hardware implementation of the algorithm. About 75% power consumption of an AES core is caused by the S-box, so reducing the power of the S-box is very efficient for the low-power design of the AES core. In this paper, the bus coding technique called sequence-switch coding (SSC) is applied in the S-box design. Input data are encoded in a certain sequence to reduce the transitions of the S-Box circuits. As a result, the power consumption in the combinational logic is brought down. The verification results show that about 10% power has been reduced averagely in the experimental S-box.