High throughput, parallelized 128-bit AES encryption in a resource-limited FPGA
Christopher Caltagirone, Kasi Anantha · 2003
This paper first highlights the mathematical properties of 128-bit AES encryption and decryption, and then uses these properties to develop a freeware, high-throughput, parallel implementation of the AES algorithm for resource-limited hardware. We compare our throughput results to advertised industry data throughput rates for comparable hardware settings. Our core can be utilized in various applications of 128-bit AES encryption and decryption. Different potential modes of operation for 128-bit AES were analyzed with respect to advantages and disadvantages in practical network settings, with a focus on Asynchronous Transfer Mode (ATM) networks.